50 nm CD Lines Etched on SiO2
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EBL100 Settings: EHT: 80kV Beam Current: 20 pA VRU: 4 Designed line width (L-Edit): 20 nm Obtained line width (SEM): 50 nm Resist: Microchem PMMA C4 (300 nm) Substrate: Silicon Oxide: SiO2 Thermal (100nm thickness) |
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Comments: Comments: PMMA C4: Coating 6000rpm 60 secs, Bake 180C 15mins Develop: 1MIBK : 3 IPA, 35 secs. No hardbake required. Oxide etched in Oxford Plasmalab 80 (recipe: smallox.prc). |
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